1. Field of the Invention
The present invention relates to a decimetor circuit composed of an FIR (finite impulse response) digital filter of a down-sampling type.
2. Description of Related Art
An A/D converter (analog-to-digital converter) typified by a .DELTA..SIGMA. type A/D converter configured to sample an analog input signal at a high speed and to convert it into digital data, incorporates therein a decimetor for converting digital data obtained by the high speed sampling, into digital data of a desired sampling frequency.
For example, one typical decimetor circuit has a function of converting digital data obtained with a sampling frequency "f" into a digital signal of a sampling frequency "f/4", by thinning out or pruning the digital data of the sampling frequency "f" with a rate of "1-out-of-4". For this purpose, the decimetor circuit includes an FIR filter circuit of 16 taps in order to prevent generation of an aliasing noise caused by the thinning-out, and a latch circuit for latching an output of the FIR filter with the frequency of "f/4". Specifically, the FIR filter circuit comprises an input terminal for receiving input data X obtained with the sampling frequency "f", and a 15-stage shift register having a first stage input connected to the input terminal and driven with a clock of the sampling frequency "f". The input terminal and an output of respective stages of the 15-stage shift register are connected to one input of sixteen multipliers, respectively. A 16-word filter coefficient memory storing 16 filter coefficients is provided to supply the 16 coefficients to the other input of the sixteen multipliers, respectively, so that the input data X and the outputs of the respective stages of the 15-stage shift register are multiplied by the 16 filter coefficients, respectively. Outputs of the sixteen multipliers are supplied to an adder so that all the outputs of the sixteen multipliers are totalized by the adder. An output of the adder is supplied to the above mentioned latch circuit, and latched by the latch circuit at a rate of "1-out-of-4", namely at a clock of the sampling frequency "f/4". An output of the latch circuit is connected to an output terminal for supplying output data Y.
In the above mentioned decimetor circuit, data transition of the input data X, the output of the adder and the output data Y is as shown in the following TABLE:
TABLE 1 __________________________________________________________________________ ##STR1## ##STR2## ##STR3## __________________________________________________________________________
As seen from the above TABLE 1, assuming that the input data X at a time "t" is x(t), the 15-stage shift register holds the data which was supplied through the input terminal and the amount of which corresponds to 15 clocks. Therefore, the input data and the output of the respective stages of the shift register can be expressed by x(t), x(t-1), . . . x(t-15). On the other hand, if the 16 filter coefficients stored in the filter coefficient memory are expressed by c(15), c(14), . . . c(0), the input and shifted data x(t), x(t-1), . . . x(t-15) are multiplied by the coefficients c(15), c(14), . . . c(0), respectively, by means of the sixteen multipliers, and totalized by the adder. Accordingly, the adder outputs data can be expressed by c(15).multidot.x(t)+c(14).multidot.x(t-1)+ . . . +c(0).multidot.x(t-15), as shown in the TABLE 1. The output data of the adder is latched by the latch circuit at the clock of the frequency "f/4".
The above mentioned conventional decimetor circuit has been required either to include sixteen multipliers and an adder capable of adding 16 items of data at once, or to include a multiplier and an adder which can execute an arithmetic operation at a speed which is 16 times as high as the sampling frequency "f" and a coefficient memory which can be accessed at a speed which is 16 times as high as the sampling frequency "f". In addition, a 15-stage shift register has also been required. As a result, the conventional decimetor circuit has been very large in size and has required to operate a high speed operation.